PIC16LC62B-04E/SO 查看數據表（PDF） - Microchip Technology
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PIC16LC62B-04E/SO Datasheet PDF : 120 Pages
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PIC16C62B/72A
FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
74
Note: Refer to Figure 13-4 for load conditions.
LSb IN
TABLE 13-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param. Symbol
No.
Characteristic
Min
Typ† Max Units Conditions
71
TscH
71A
SCK input high time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns Note 1
72
TscL
72A
SCK input low time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns Note 1
73
TdiV2scH, Setup time of SDI data input to SCK
TdiV2scL edge
100
— — ns
73A
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
— — ns
75
TdoR
76
TdoF
SDO data output rise
time
PIC16CXX
PIC16LCXX
SDO data output fall time
—
10 25 ns
20 45 ns
—
10 25 ns
78
TscR
SCK output rise time
(master mode)
PIC16CXX
PIC16LCXX
—
10 25 ns
20 45 ns
79
TscF
SCK output fall time (master mode)
—
10 25 ns
80
TscH2doV, SDO data output valid PIC16CXX
TscL2doV after SCK edge
PIC16LCXX
—
— 50 ns
— 100 ns
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
— — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS35008B-page 96
Preliminary
© 1998 Microchip Technology Inc.
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