PIC16C774T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC16C774T-I/SO

28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D

Microchip Technology 

PIC16C77X

9.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI). The USART can be con-

figured as a full duplex asynchronous system that can

communicate with peripheral devices such as CRT ter-

minals and personal computers, or it can be configured

as a half duplex synchronous system that can commu-

nicate with peripheral devices such as A/D or D/A inte-

grated circuits, Serial EEPROMs etc.

The USART can be configured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to

be set in order to configure pins RC6/TX/CK and RC7/

RX/DT as the Universal Synchronous Asynchronous

Receiver Transmitter.

The USART module also has a multi-processor com-

munication capability using 9-bit address detection.

FIGURE 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1

CSRC TX9 TXEN SYNC

—

BRGH TRMT

bit7

bit 7:

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

CSRC: Clock Source Select bit

Asynchronous mode

Don’t care

Synchronous mode

1 = Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

TXEN: Transmit Enable bit

1 = Transmit enabled

0 = Transmit disabled

Note: SREN/CREN overrides TXEN in SYNC mode.

SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

Unimplemented: Read as '0'

BRGH: High Baud Rate Select bit

Asynchronous mode

1 = High speed

0 = Low speed

Synchronous mode

Unused in this mode

TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

TX9D: 9th bit of transmit data. Can be parity bit.

R/W-0

TX9D

bit0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

 1999-2013 Microchip Technology Inc.

Advance Information

DS30275B-page 97

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