PIC16F1828T-I/SL 查看數據表（PDF） - Microchip Technology

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PIC16F1828T-I/SL

28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16(L)F1824/1828

25.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating

at a different speed than when in Full Power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the

MSSP1 clock is much faster than the system clock.

In Slave mode, when MSSP1 interrupts are enabled,

after the master completes sending data, an MSSP1

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP1 inter-

rupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all 8 bits have been received, the

MSSP1 interrupt flag bit will be set and if enabled, will

wake the device.

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ANSELA

—

—

—

ANSA4

—

ANSA2

ANSA1

ANSELB(1)

ANSELC

ANSB7

ANSC7(1)

ANSB6

ANSC6(1)

ANSB5

—

ANSB4

—

—

ANSC3

—

ANSC2

—

ANSC1

APFCON0

RXDTSEL SDOSEL(2) SSSEL(2)

—

T1GSEL

TXCKSEL

—

INLVLA(3)

—

—

INLVLA5

INLVLA4

INLVLA3

INLVLA2

INLVLA1

INLVLA(4)

—

—

INLVLA5

INLVLA4

INLVLA3

INLVLA2

INLVLA1

INLVLB(1)

INLVLB7

INLVLB6

INLVLB5

INLVLB4

—

—

—

INLVLC(3)

INLVLC7(1) INLVLC6(1) INLVLC5

INLVLC4

INLVLC3

INLVLC2

INLVLC1

INLVLC(4)

INLVLC7(1) INLVLC6(1) INLVLC5

INLVLC4

INLVLC3

INLVLC2

INLVLC1

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register

SSP1CON1

WCOL

SSPOV

SSPEN

CKP

SSPM<3:0>

SSP1CON3

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

SSP1STAT

SMP

CKE

D/A

P

S

R/W

UA

TRISA(3)

—

—

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA(4)

—

—

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISB(1)

TRISB7

TRISB6

TRISB5

TRISB4

—

—

—

TRISC(3)

TRISC7(1) TRISC6(1)

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC(4)

TRISC7(1) TRISC6(1)

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

Legend:

*

Note 1:

2:

3:

4:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.

Page provides register information.

PIC16F/LF1828 only.

PIC16F/LF1824 only.

Unshaded cells apply to PIC16F/LF1828 only.

Unshaded cells apply to PIC16F/LF1824 only.

Bit 0

ANSA0

—

ANSC0

—

INLVLA0

INLVLA0

—

INLVLC0

INLVLC0

IOCIF

TMR1IE

TMR1IF

DHEN

BF

TRISA0

TRISA0

—

TRISC0

TRISC0

Register on

Page

127

133

133

122

128

128

133

139

139

93

94

97

247*

293

295

292

126

126

132

132

132

DS41419B-page 254

Preliminary

 2010 Microchip Technology Inc.

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