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PIC16F688T-I/ST 查看數據表(PDF) - Microchip Technology

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PIC16F688T-I/ST Datasheet PDF : 202 Pages
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PIC16F688
FIGURE 11-8:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT (3)
(4)
INT pin
INTF Flag
(1)
(INTCON<1>)
(1)
(5)
GIE bit
(INTCON<7>)
Interrupt Latency (2)
Instruction Flow
PC
Instruction
Fetched
PC
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC - 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1:
2:
3:
4:
5:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
PIE1
PIR1
Legend:
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF 0000 000x
EEIE ADIE RCIE C2IE
C1IE OSFIE TXIE TMR1IE 0000 0000
EEIF
ADIF RCIF
C2IF
C1IF OSFIF TXIF TMR1IF 0000 0000
x = unknown, u = unchanged, = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
0000 000x
0000 0000
0000 0000
© 2007 Microchip Technology Inc.
DS41203D-page 121

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