PIC16F690T-ESS 查看數據表（PDF） - Microchip Technology

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PIC16F690T-ESS

20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC16F631/677/685/687/689/690

TABLE 2-2: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Page

Bank 1

80h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205

81h OPTION_REG RABPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

37,205

82h PCL

Program Counter’s (PC) Least Significant Byte

0000 0000 44,205

83h STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 36,205

84h FSR

Indirect Data Memory Address Pointer

xxxx xxxx 44,205

85h TRISA

—

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 59,205

86h TRISB

TRISB7 TRISB6 TRISB5 TRISB4

—

—

—

—

1111 ---- 70,206

87h TRISC

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 76,205

88h

—

Unimplemented

—

—

89h

—

Unimplemented

—

—

8Ah PCLATH

8Bh INTCON

8Ch PIE1

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 44,205

GIE

PEIE

T0IE

INTE

RABIE

T0IF

INTF

RABIF(1) 0000 000x

38,205

—

ADIE(4) RCIE(2) TXIE(2) SSPIE(5) CCP1IE(3) TMR2IE(3) TMR1IE -000 0000

39,206

8Dh PIE2

OSFIE

C2IE

C1IE

EEIE

—

—

—

—

0000 ---- 40,206

8Eh PCON

—

—

ULPWUE SBOREN

—

—

POR

BOR --01 --qq 43,206

8Fh OSCCON

—

IRCF2 IRCF1 IRCF0 OSTS

HTS

LTS

SCS -110 q000 48,206

90h OSCTUNE

—

—

—

TUN4

TUN3

TUN2

TUN1

TUN0 ---0 0000 52,206

91h

—

Unimplemented

92h PR2(3)

Timer2 Period Register

93h SSPADD(5, 7) Synchronous Serial Port (I2C mode) Address Register

93h SSPMSK(5, 7)

MSK7

MSK6

MSK5

MSK4

MSK3

94h SSPSTAT(5)

SMP

CKE

D/A

P

S

95h WPUA(6)

—

—

WPUA5 WPUA4

—

MSK2

R/W

WPUA2

MSK1

UA

WPUA1

MSK0

BF

WPUA0

—

1111 1111

0000 0000

1111 1111

0000 0000

--11 -111

—

91,206

188,206

191,206

180,206

62,206

96h IOCA

—

—

IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 62,206

97h WDTCON

98h TXSTA(2)

99h SPBRG(2)

9Ah SPBRGH(2)

9Bh BAUDCTL(2)

—

CSRC

BRG7

BRG15

ABDOVF

—

TX9

BRG6

BRG14

RCIDL

—

TXEN

BRG5

BRG13

—

WDTPS3 WDTPS2

SYNC SENDB

BRG4 BRG3

BRG12 BRG11

SCKP BRG16

WDTPS1

BRGH

BRG2

BRG10

—

WDTPS0 SWDTEN

TRMT

TX9D

BRG1

BRG0

BRG9

BRG8

WUE ABDEN

---0 1000

0000 0010

0000 0000

0000 0000

01-0 0-00

213,206

160,206

163,206

163,206

162,206

9Ch

—

Unimplemented

—

—

9Dh

—

Unimplemented

—

—

9Eh ADRESL(4)

A/D Result Register Low Byte

xxxx xxxx 115,206

9Fh ADCON1(4)

—

ADCS2 ADCS1 ADCS0

—

—

—

—

-000 ---- 114,206

Legend:

Note 1:

2:

3:

4:

5:

6:

7:

– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

Accessible only when SSPCON register bits SSPM<3:0> = 1001.

© 2008 Microchip Technology Inc.

DS41262E-page 33

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