PIC16F72T-IP 查看數據表（PDF） - Microchip Technology
零件编号
产品描述 (功能)
生产厂家
PIC16F72T-IP Datasheet PDF : 136 Pages
| |||
8.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
CCPR1L
CCP1CON<5:4>
CCPR1H (Slave)
Comparator
R
TMR2
(Note 1)
S
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Q
RC2/CCP1
TRISC<2>
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PIC16F72
8.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the
formula in Equation 8-1.
EQUATION 8-1: PWM PERIOD
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 6.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different
frequency than the PWM output.
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. Equation 8-2 is used to
calculate the PWM duty cycle in time.
EQUATION 8-2: PWM DUTY CYCLE
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
© 2007 Microchip Technology Inc.
DS39597C-page 41
Share Link: 