PIC16F724-I/SP 查看數據表（PDF） - Microchip Technology
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PIC16F724-I/SP Datasheet PDF : 302 Pages
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PIC16F72X/PIC16LF72X
4.5.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 7
R/W-0
CCP2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
OPTION_REG RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.
DS41341E-page 50
© 2009 Microchip Technology Inc.
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