PIC16F753-I/SLQTP 查看數據表（PDF） - Microchip Technology

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PIC16F753-I/SLQTP

14/16-Pin, Flash-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16F753/HV753

TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register on

Page

PCON

—

—

—

—

—

—

POR

BOR

24

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

17

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Shaded cells are not used by BOR.

19.3.5 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

• PWRT time-out is invoked after POR has expired.

• OST is activated after the PWRT time-out has

expired.

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in EC

mode with PWRTE bit erased (PWRT disabled), there

will be no time-out at all. Figure 19-4, Figure 19-5 and

Figure 19-6 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 19-5). This is useful for testing purposes or

to synchronize more than one PIC16F753/HV753

device operating in parallel.

Table 19-5 shows the Reset conditions for some

special registers, while Table 19-4 shows the Reset

conditions for all the registers.

19.3.6 POWER CONTROL (PCON)

REGISTER

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset occurred

last.

Bit 0 is BOR (Brown-out). BOR is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent Resets to see if BOR = 0, indicating that

a Brown-out has occurred. The BOR Status bit is a

“don’t care” and is not necessarily predictable if the

brown-out circuit is disabled (BOREN<1:0> = 00 in the

Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent Reset, if POR is ‘0’, it will indicate that a Power-

on Reset has occurred (i.e., VDD may have gone too

low).

For more information, see Section 19.3.4 “Brown-out

Reset (BOR)”.

FIGURE 19-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TIOSCST

DS40001709A-page 166

Preliminary

 2013 Microchip Technology Inc.

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