PIC16C71X
4.2.2.5 PIR1 REGISTER
Applicable Devices 710 71 711 715
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
U-0
U-0
—
ADIF
—
—
—
—
bit7
bit 7: Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-0: Unimplemented: Read as '0'
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
U-0
—
—
R = Readable bit
bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
© 1997 Microchip Technology Inc.
DS30272A-page 21