PIC16(L)F1512/3
FIGURE 16-1:
ADC BLOCK DIAGRAM
VDD
FVR
ADPREF = 0x
ADPREF = 11
VREF+ ADPREF = 10
AN0
AN1
AN2
VREF+/AN3
AN4
Reserved
Reserved
Reserved
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
Reserved
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
ADC
GO/DONE
10
ADON(1)
ADFM
0 = Left Justify
1 = Right Justify
16
VSS
ADRESxH(3) ADRESxL(4)
Reserved
VREFH (ADC positive reference)
VREFL (ADC negative reference)
Reserved
Temp Indicator
Reserved
FVR Buffer1
11001
11010
11011
11100
11101
11110
11111
CHS<4:0>(2)
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See AADCON0 register (Register 16-7) for detailed analog channel selection per device.
3: ADRES0H and AADRES0H are the same register in two locations, Bank 1 and Bank 14. See Table 3-9.
4: ADRES0L and AADRES0L are the same register in two locations, Bank 1 and Bank 14. See Table 3-9.
DS40001624C-page 124
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