PIC16LF1512-I/SP 查看數據表（PDF） - Microchip Technology

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PIC16LF1512-I/SP

28-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

PIC16(L)F1512/3

REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0

bit 7

W-0/0

W-0/0

W-0/0

W-0/0

W-0/0

Program Memory Control Register 2

W-0/0

W-0/0

bit 0

Legend:

R = Readable bit

S = Bit can only be set

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

PMCON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register on

Page

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

69

PMCON1

—

CFGS

LWLO

FREE

WRERR WREN

WR

RD

98

PMCON2

Program Memory Control Register 2

99

PMADRL

PMADRL<7:0>

97

PMADRH

—

PMADRH<6:0>

97

PMDATL

PMDATL<7:0>

97

PMDATH

—

—

PMDATH<5:0>

97

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Name Bits Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3 Bit 10/2

Bit 9/1

Bit 8/0

Register

on Page

13:8

—

FCMEN

IESO CLKOUTEN

BOREN<1:0>

—

CONFIG1

36

7:0

CP

MCLRE PWRTE

WDTE<1:0>

FOSC<2:0>

13:8

—

—

LVP

DEBUG

LPBOR

BORV STVREN

—

CONFIG2

7:0

—

—

—

VCAPEN(1)

—

—

38

WRT<1:0>

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

 2012-2014 Microchip Technology Inc.

DS40001624C-page 99

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