PIC18LF1320-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18LF1320-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

17.7 A/D Conversions

Figure 17-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are cleared. A conversion is started after the follow-

ing instruction to allow entry into Low-Power Sleep

mode before the conversion begins.

Figure 17-4 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are set to ‘010’ and selecting a 4 TAD acquisition

time before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will NOT be updated with the partially completed

A/D conversion sample. This means the

ADRESH:ADRESL registers will continue to contain

the value of the last completed conversion (or the last

value written to the ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2 TAD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

FIGURE 17-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion Starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 17-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TACQT Cycles

TAD Cycles

123412345678

Automatic

Acquisition

Time

b9 b8 b7 b6 b5 b4 b3

Conversion Starts

(Holding capacitor is disconnected)

9 10 11

b2 b1 b0

Set GO bit

(Holding capacitor continues

acquiring input)

Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

© 2007 Microchip Technology Inc.

DS39605F-page 163

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