PIC18LF1320-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18LF1320-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

19.5 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other PIC

devices.

The user program memory is divided into three blocks.

One of these is a boot block of 512 bytes. The remain-

der of the memory is divided into two blocks on binary

boundaries.

Each of the three blocks has three protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 19-5 shows the program memory organization

for 4 and 8-Kbyte devices and the specific code protec-

tion bit associated with each block. The actual locations

of the bits are summarized in Table 19-3.

FIGURE 19-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320

Block Code

Protection

Controlled By:

MEMORY SIZE/DEVICE

Address 4 Kbytes

8 Kbytes Address

Range (PIC18F1220) (PIC18F1320) Range

Block Code

Protection

Controlled By:

CPB, WRTB, EBTRB

000000h

0001FFh

000200h

CP0, WRT0, EBTR0

0007FFh

000800h

CP1, WRT1, EBTR1

000FFFh

001000h

Boot Block

Block 0

Block 1

Boot Block

000000h

0001FFh

CPB, WRTB, EBTRB

000200h

Block 0

CP0, WRT0, EBTR0

000FFFh

001000h

Block 1

CP1, WRT1, EBTR1

(Unimplemented

Memory Space)

Unimplemented

Read ‘0’s

001FFFh

002000h

1FFFFFh

Unimplemented

Read ‘0’s

(Unimplemented

Memory Space)

1FFFFFh

TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

300008h CONFIG5L —

—

—

—

—

300009h CONFIG5H CPD

CPB

—

—

—

30000Ah CONFIG6L —

—

—

—

—

30000Bh CONFIG6H WRTD WRTB WRTC

—

—

30000Ch CONFIG7L —

—

—

—

—

30000Dh CONFIG7H —

EBTRB

—

—

—

Legend: Shaded cells are unimplemented.

Bit 2

—

—

—

—

—

—

Bit 1

CP1

—

WRT1

—

EBTR1

—

Bit 0

CP0

—

WRT0

—

EBTR0

—

© 2007 Microchip Technology Inc.

DS39605F-page 185

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