PIC18LF4439-I/P 查看數據表（PDF） - Microchip Technology

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PIC18LF4439-I/P

Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

Microchip Technology 

PIC18FXX39

8.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Priority registers (IPR1, IPR2). The operation of

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

For PIC18FXX39 devices, the Motor Control kernel

requires that the Timer2 to PR2 match interrupt be the

only high priority interrupt. Failure to do this may result

in unpredictable operation of the kernel or the entire

microcontroller.

In practical terms, this means:

• Interrupt priority levels are enabled (IPEN = 1);

• High priority interrupts are enabled

(INTCON<7> = 1);

• Timer2 interrupt is enabled and set as high priority

(PIE1<1> and IPR<1> = 1); and

• all other interrupts are disabled (INTCON or PIR

bits = 0), or set as low priority (IPR bits = 0).

Note:

Configuring the interrupts is automatically

done by the API method void

ProMPT_Init(PWMfrequency). It is the

user’s responsibility to make certain that

this method is called at the very beginning

of the application.

REGISTER 8-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

U-1

PSPIP(1,2) ADIP(2) RCIP(2) TXIP(2) SSPIP(2)

—

bit 7

R/W-1 R/W-1

TMR2IP(3) TMR1IP(2)

bit 0

bit 7

PSPIP(1,2): Parallel Slave Port Read/Write Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6

ADIP(2): A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5

RCIP(2): USART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4

TXIP(2): USART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3

SSPIP(2): Master Synchronous Serial Port Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2

Unimplemented: Read as ‘1’

bit 1

TMR2IP(3): TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

TMR1IP(2): TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Note 1: This bit is reserved on PIC18F2X39 devices.

2: Maintain this bit cleared (= 0).

3: This bit is reserved for use by the ProMPT kernel; always maintain this bit set (= 1).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485B-page 78

Preliminary

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