PIC18LF4550T-I/SO 查看數據表（PDF） - Microchip Technology

零件编号

产品描述 (功能)

生产厂家

PIC18LF4550T-I/SO

28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F2455/2550/4455/4550

9.5 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Priority registers (IPR1 and IPR2). Using the

priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

SPPIP(1)

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

CCP1IP

R/W-1

TMR2IP

R/W-1

TMR1IP

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1)

1 = High priority

0 = Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2

CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.

DS39632E-page 108

© 2009 Microchip Technology Inc.

Share Link: