PIC18F45J50-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

TABLE 10-5: PORTB I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

I/O

Type

Description

RB0/AN12/

INT0/RP3

RB0

1

I

TTL PORTB<0> data input; weak pull-up when RBPU bit is

cleared. Disabled when analog input is enabled.(1)

0

O DIG LATB<0> data output; not affected by analog input.

AN12

1

I

ANA A/D Input Channel 12.(1)

INT0

1

I

ST External Interrupt 0 input.

RP3

1

I

ST Remappable Peripheral Pin 3 input.

0

O DIG Remappable Peripheral Pin 3 output.

RB1/AN10/

RB1

1

I

TTL PORTB<1> data input; weak pull-up when RBPU bit is

PMBE/RTCC/

cleared. Disabled when analog input is enabled.(1)

RP4

0

O DIG LATB<1> data output; not affected by analog input.

AN10

1

I

ANA A/D Input Channel 10.(1)

PMBE(3)

0

O DIG Parallel Master Port byte enable output.

RTCC

0

O DIG Real-Time Clock Calender output.

RP4

1

I

ST Remappable Peripheral Pin 4 input.

0

O DIG Remappable Peripheral Pin 4 output.

RB2/AN8/

RB2

CTED1/PMA3/

VMO/REFO/

RP5

AN8

1

I

TTL PORTB<2> data input; weak pull-up when RBPU bit is

cleared. Disabled when analog input is enabled.(1)

0

O DIG LATB<2> data output; not affected by analog input.

1

I

ANA A/D Input Channel 8.(1)

CTED1

1

PMA3(3)

0

I

ST CTMU Edge 1 input.

O DIG Parallel Master Port address.

VMO

0

O DIG External USB transceiver D – data output.

REFO

0

O DIG Reference output clock.

RP5

1

I

ST Remappable Peripheral Pin 5 input.

0

O DIG Remappable Peripheral Pin 5 output.

RB3/AN9/

RB3

CTED2/PMA2/

VPO/RP6

0

O DIG LATB<3> data output; not affected by analog input.

1

I

TTL PORTB<3> data input; weak pull-up when RBPU bit is

cleared. Disabled when analog input is enabled.(1)

AN9

1

I

ANA A/D Input Channel 9.(1)

CTED2

1

I

ST CTMU Edge 2 input.

PMA2(3)

0

O DIG Parallel Master Port address.

VPO

0

I

DIG External USB transceiver D+ data output.

RP6

1

I

ST Remappable Peripheral Pin 6 input.

0

O DIG Remappable Peripheral Pin 6 output.

Legend:

Note 1:

2:

3:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level

input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)

Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting

the appropriate bits in the ANCONx register first.

All other pin functions are disabled when ICSP™ or MPLAB® ICD are enabled.

This functionality is only available on 44-pin devices.

DS39931D-page 140

 2011 Microchip Technology Inc.

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