PIC18F45J50-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

REGISTER 18-4: PSTRxCON: PULSE STEERING CONTROL REGISTER (ACCESS FBFh, FB9h)(1)

R/W-0

CMPL1

bit 7

R/W-0

CMPL0

U-0

R/W-0

R/W-0

—

STRSYNC

STRD

R/W-0

STRC

R/W-0

STRB

R/W-1

STRA

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits

1 = Modulated output pin toggles between PxA and PxB for each period

0 = Complementary output assignment disabled; STR<D:A> bits are used to determine Steering mode

Unimplemented: Read as ‘0’

STRSYNC: Steering Sync bit

1 = Output steering update occurs on next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

STRD: Steering Enable bit D

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxD pin is assigned to port pin

STRC: Steering Enable bit C

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxC pin is assigned to port pin

STRB: Steering Enable bit B

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to port pin

STRA: Steering Enable bit A

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxA pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11, and

PxM<1:0> = 00.

 2011 Microchip Technology Inc.

DS39931D-page 265

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