PIC18F45J50-I/SOSQTP 查看數據表（PDF） - Microchip Technology

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PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

CPFSGT

Compare f with W, Skip if f > W

Syntax:

CPFSGT f {,a}

Operands:

Operation:

0  f  255

a  [0,1]

(f) –W),

skip if (f) > (W)

(unsigned comparison)

Status Affected:

None

Encoding:

Description:

0110 010a ffff ffff

Compares the contents of data mem-

ory location, ‘f’, to the contents of the W

by performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words:

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 28.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Decode

Read

Process

register ‘f’

Data

If skip:

Q1

Q2

Q3

No

No

No

operation operation operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

No

No

No

operation operation operation

No

No

No

operation operation operation

Q4

No

operation

Q4

No

operation

Q4

No

operation

No

operation

Example:

HERE

CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC

=

W

=

After Instruction

If REG



PC

=

If REG



PC

=

Address (HERE)

?

W;

Address (GREATER)

W;

Address (NGREATER)

CPFSLT

Compare f with W, Skip if f < W

Syntax:

CPFSLT f {,a}

Operands:

Operation:

0  f  255

a  [0,1]

(f) –W),

skip if (f) < (W)

(unsigned comparison)

Status Affected:

None

Encoding:

0110 000a ffff ffff

Description:

Compares the contents of data mem-

ory location, ‘f’, to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words:

1

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Decode

Read

register ‘f’

Process

Data

If skip:

Q1

Q2

Q3

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Q4

No

operation

Q4

No

operation

Q4

No

operation

No

operation

Example:

HERE

NLESS

LESS

CPFSLT REG, 1

:

:

Before Instruction

PC

=

W

=

After Instruction

If REG

<

PC

=

If REG



PC

=

Address (HERE)

?

W;

Address (LESS)

W;

Address (NLESS)

 2011 Microchip Technology Inc.

DS39931D-page 453

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