PIC18LF2610T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC18LF2610T-I/SO

28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2X1X/4X1X

FIGURE 17-7:

RX (pin)

Rcv Shift Reg

Rcv Buffer Reg

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

ASYNCHRONOUS RECEPTION

Start

bit bit 0 bit 1

Start

bit 7/8 Stop bit bit 0

bit

Word 1

RCREG

Start

bit 7/8 Stop bit

bit

Word 2

RCREG

bit 7/8 Stop

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing

the OERR (overrun) bit to be set.

TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

PIR1

PIE1

IPR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

49

PSPIF(1) ADIF

RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

52

PSPIE(1) ADIE

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE 52

PSPIP(1) ADIP

RCIP

TXIP SSPIP CCP1IP TMR2IP TMR1IP 52

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D

51

RCREG

EUSART Receive Register

51

TXSTA

CSRC

TX9

TXEN SYNC SENDB BRGH TRMT TX9D

51

BAUDCON ABDOVF RCIDL

—

SCKP BRG16

—

WUE ABDEN

51

SPBRGH EUSART Baud Rate Generator Register, High Byte

51

SPBRG

EUSART Baud Rate Generator Register, Low Byte

51

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39636C-page 203

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