PIC18F4515T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC18F4515T-I/SO

28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2X1X/4X1X

FIGURE 22-6:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2515/2610/4515/4610

MEMORY SIZE/DEVICE

48 Kbytes

64 Kbytes

Address

(PIC18F2515/4515) (PIC18F2610/4610) Range

Block Code Protection

Controlled By:

Boot Block

Block 0

Block 1

Block 2

Boot Block

Block 0

Block 1

Block 2

Block 3

000000h

0007FFh

000800h

003FFFh

004000h

007FFFh

008000h

00BFFFh

00C000h

00FFFFh

010000h

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

CP1, WRT1, EBTR1

CP2, WRT2, EBTR2

CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

Unimplemented

Read ‘0’s

(Unimplemented Memory Space)

1FFFFFh

TABLE 22-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

300008h

300009h

30000Ah

30000Bh

30000Ch

30000Dh

Legend:

Note 1:

2:

CONFIG5L

—

—

—

—

CP3(1,2)

CONFIG5H

—

CPB

—

CONFIG6L

—

—

—

—

—

—

WRT3(1,2)

CONFIG6H

—

CONFIG7L

—

WRTB

—

WRTC

—

—

—

—

EBTR3(1,2)

CONFIG7H

—

EBTRB

—

—

—

Shaded cells are unimplemented.

Unimplemented in PIC18F2410/4410 devices; maintain this bit set.

Unimplemented in PIC18F2515/4515 devices; maintain this bit set.

CP2(1)

—

WRT2(1)

—

EBTR2(1)

—

Bit 1

CP1

—

WRT1

—

EBTR1

—

Bit 0

CP0

—

WRT0

—

EBTR0

—

DS39636C-page 252

Preliminary

© 2007 Microchip Technology Inc.

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