PIC18F66K22-I/PTRSL 查看數據表（PDF） - Microchip Technology

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PIC18F66K22-I/PTRSL

64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

Microchip Technology 

PIC18F87K22 FAMILY

SUBLW

Subtract W from Literal

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

SUBLW k

0 k 255

k – (W) W

N, OV, C, DC, Z

0000 1000 kkkk kkkk

W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

1

1

Q2

Read

literal ‘k’

Q3

Process

Data

Q4

Write to

W

Example 1:

SUBLW 02h

Before Instruction

W

= 01h

C

=?

After Instruction

W

= 01h

C

= 1 ; result is positive

Z

=0

N

=0

Example 2:

SUBLW 02h

Before Instruction

W

= 02h

C

=?

After Instruction

W

= 00h

C

= 1 ; result is zero

Z

=1

N

=0

Example 3:

SUBLW 02h

Before Instruction

W

= 03h

C

=?

After Instruction

W

= FFh ; (2’s complement)

C

= 0 ; result is negative

Z

=0

N

=1

 2009-2011 Microchip Technology Inc.

SUBWF

Subtract W from f

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

SUBWF f {,d {,a}}

0 f 255

d  [0,1]

a  [0,1]

(f) – (W) dest

N, OV, C, DC, Z

0101 11da ffff ffff

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the result

is stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 29.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example 1:

SUBWF REG, 1, 0

Before Instruction

REG

W

C

=3

=2

=?

After Instruction

REG

W

C

Z

N

=1

=2

=1

=0

=0

; result is positive

Example 2:

SUBWF REG, 0, 0

Before Instruction

REG

W

C

=2

=2

=?

After Instruction

REG

W

C

Z

N

=2

=0

=1

=1

=0

; result is zero

Example 3:

SUBWF REG, 1, 0

Before Instruction

REG =

W

=

C

=

After Instruction

REG =

W

=

C

=

Z

=

N

=

1

2

?

FFh ;(2’s complement)

2

0 ; result is negative

0

1

DS39960D-page 467

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