PIC18LF4420T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC18LF4420T-I/SO

28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2420/2520/4420/4520

FIGURE 17-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

SDA

TBRG

TBRG

SCL

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SEN

BCLIF

SCL = 0 before BRG time-out,

bus collision occurs. Set BCLIF.

S

‘0’

SSPIF ‘0’

SCL = 0 before SDA = 0,

bus collision occurs. Set BCLIF.

Interrupt cleared

in software

‘0’

‘0’

FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SDA = 0, SCL = 1

Set S

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

Set SSPIF

SCL

SEN

BCLIF

S

SCL pulled low after BRG

time-out

Set SEN, enable START

sequence if SDA = 1, SCL = 1

‘0’

S

SSPIF

SDA = 0, SCL = 1,

set SSPIF

Interrupts cleared

in software

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 197

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