PIC18LF4420T-I/SO 查看數據表（PDF） - Microchip Technology

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PIC18LF4420T-I/SO

28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2420/2520/4420/4520

FIGURE 26-22: A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

Q4

130

A/D CLK 132

A/D DATA

9

8 7 ... ... 2

1

0

ADRES

ADIF

GO

SAMPLE

OLD_DATA

SAMPLING STOPPED

NEW_DATA

TCY

DONE

Note 1:

2:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 26-25: A/D CONVERSION REQUIREMENTS

Param

No.

Symbol

Characteristic

Min Max Units

Conditions

130 TAD

A/D Clock Period

PIC18FXXXX

PIC18LFXXXX

0.7 25.0(1) µs TOSC based, VREF ≥ 3.0V

1.4 25.0(1) µs VDD = 2.0V;

TOSC based, VREF full range

PIC18FXXXX

TBD

1

µs A/D RC mode

PIC18LFXXXX

TBD

3

µs VDD = 2.0V; A/D RC mode

131 TCNV Conversion Time

11

12

TAD

(not including acquisition time) (Note 2)

132 TACQ Acquisition Time (Note 3)

1.4

—

TBD

—

µs -40°C to +85°C

µs 0°C ≤ to ≤ +85°C

135 TSWC Switching Time from Convert → Sample

— (Note 4)

TBD TDIS Discharge Time

0.2

—

µs

Legend: TBD = To Be Determined

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES register may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 359

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