PIC18LF4520T-ISP 查看數據表（PDF） - Microchip Technology
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PIC18LF4520T-ISP
Microchip Technology
PIC18LF4520T-ISP Datasheet PDF : 390 Pages
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PIC18F2420/2520/4420/4520
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
Timer0 Register, High Byte
Timer0 Register, Low Byte
TMR0ON T08BIT
IDLEN
IRCF2
VDIRMAG
—
—
—
IPEN
SBOREN(1)
T0CS
IRCF1
IRVST
—
—
TMR1H
TMR1L
Timer1 Register, High Byte
Timer1 Register, Low Bytes
T0SE
IRCF0
HLVDEN
—
RI
PSA
OSTS
HLVDL3
—
TO
T0PS2
IOFS
HLVDL2
—
PD
T0PS1
SCS1
HLVDL1
—
POR
0000 0000 50, 125
xxxx xxxx 50, 125
T0PS0 1111 1111 50, 123
SCS0 0100 q000 30, 50
HLVDL0 0-00 0101 50, 245
SWDTEN --- ---0 50, 259
BOR
0q-1 11q0 42, 48,
102
xxxx xxxx 50, 131
xxxx xxxx 50, 131
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN
Timer2 Register
Timer2 Period Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
SSP Receive Buffer/Transmit Register
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
SMP
CKE
D/A
P
S
R/W
UA
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
GCEN ACKSTAT ACKDT
A/D Result Register, High Byte
A/D Result Register, Low Byte
ACKEN
RCEN
PEN
RSEN
TMR1ON 0000 0000 50, 127
0000 0000 50, 134
1111 1111 50, 134
T2CKPS0 -000 0000 50, 133
xxxx xxxx 50, 169,
170
0000 0000 50, 170
BF
0000 0000 50, 162,
171
SSPM0 0000 0000 50, 163,
172
SEN 0000 0000 50, 173
xxxx xxxx 51, 232
xxxx xxxx 51, 232
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
—
—
CHS3
CHS2
—
—
VCFG1
VCFG0
ADFM
—
ACQT2
ACQT1
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CHS1
PCFG3
ACQT0
CCP1M3
CCPR2H
CCPR2L
CCP2CON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
Capture/Compare/PWM Register 2, High Byte
Capture/Compare/PWM Register 2, Low Byte
—
—
DC2B1
DC2B0
ABDOVF
PRSEN
RCIDL
PDC6(2)
—
PDC5(2)
SCKP
PDC4(2)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
CVREN
CVROE
CVRR
CVRSS
C2OUT
C1OUT
C2INV
C1INV
Timer3 Register, High Byte
Timer3 Register, Low Byte
CCP2M3
BRG16
PDC3(2)
PSSAC1
CVR3
CIS
CHS0
PCFG2
ADCS2
CCP1M2
CCP2M2
—
PDC2(2)
PSSAC0
CVR2
CM2
GO/DONE
PCFG1
ADCS1
CCP1M1
CCP2M1
WUE
PDC1(2)
PSSBD1(2)
CVR1
CM1
ADON --00 0000 51, 223
PCFG0 --00 0qqq 51, 224
ADCS0 0-00 0000 51, 225
xxxx xxxx 51, 140
xxxx xxxx 51, 140
CCP1M0 0000 0000 51, 139,
147
xxxx xxxx 51, 140
xxxx xxxx 51, 140
CCP2M0 --00 0000 51, 139
ABDEN
PDC0(2)
PSSBD0(2)
01-0 0-00
0000 0000
0000 0000
51, 204
51, 156
51, 157
CVR0 0000 0000 51, 239
CM0 0000 0111 51, 233
xxxx xxxx 51, 137
xxxx xxxx 51, 137
T3CON
Legend:
Note 1:
2:
3:
4:
5:
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 135
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS39631A-page 65
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