PIC18LF4420T-I/SO 查看數據表（PDF） - Microchip Technology

零件编号

产品描述 (功能)

生产厂家

PIC18LF4420T-I/SO

28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2420/2520/4420/4520

7.6 Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

configuration words. External read and write

operations are disabled if code protection is enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

7.7 Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are blocked

during the Power-up Timer period (TPWRT,

parameter 33).

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch or software malfunction.

7.8 Using the Data EEPROM

The data EEPROM is a high endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than specification D124. If this is

not the case, an array refresh must be performed. For

this reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

Note:

If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

EXAMPLE 7-3:

Loop

CLRF

BCF

BCF

BCF

BSF

BSF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BTFSC

BRA

INCFSZ

BRA

BCF

BSF

DATA EEPROM REFRESH ROUTINE

EEADR

EECON1, CFGS

EECON1, EEPGD

INTCON, GIE

EECON1, WREN

EECON1, RD

55h

EECON2

0AAh

EECON2

EECON1, WR

EECON1, WR

$-2

EEADR, F

LOOP

; Start at address 0

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Wait for write to complete

; Increment address

; Not zero, do it again

EECON1, WREN

INTCON, GIE

; Disable writes

; Enable interrupts

DS39631A-page 86

Preliminary

 2004 Microchip Technology Inc.

Share Link: