PSD511B1-C-90UI 查看數據表（PDF） - STMicroelectronics

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PSD511B1-C-90UI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

Counter / Timer

Registers

(Cont.)

PSD5XX Family

9.6.2.6 Status Flags Register

There are eight READ-ONLY status flags. The lower four bits represent Freeze

Acknowledge bits.

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

*

*

*

*

FrezAck3

NOTES: At RESET all these bits intialize as 0's.

* = Not used.

Bit 2

FrezAck2

Bit 1

FrezAck1

Bit 0

FrezAck0

FrezAck Bits

These Freeze Acknowledge bits are useful in the Freeze/Freeze Acknowledge protocol.

After the Microcontroller senses that the FrezAck bit is being set it proceeds to access the

Image Register for a read or write operation.

FrezAck0 Bit:

When this bit is

1: Image Register Access is granted.

0: Image Register Access is not granted.

FrezAck1 Bit:

When this bit is

1: Image Register Access is granted.

0: Image Register Access is not granted.

FrezAck2 Bit:

When this bit is

1: Image Register Access is granted.

0: Image Register Access is not granted.

FrezAck3 Bit:

When this bit is

1: Image Register Access is granted.

0: Image Register Access is not granted.

DLCY Register:

Bits <4:0> of the DLCY register are used to assign Delay Cycles to the Counter/Timer.

Various Clock Scaling values possible are 0 through 31 (decimal).

At RESET these bits initialize as 0. If necessary, the user has the option to set these bits up

to generate Delay Cycles (DLCY) to scale down the Counter/Timer clock (see Table 24).

Bit 7

Bit 6

*

*

NOTE: * = Not used.

Bit 5

*

Bit 4

DLCY4

Bit 3

DLCY3

Bit 2

DLCY2

Bit 1

DLCY1

Bit 0

DLCY0

89

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