PSD802G1V-B-20UI 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
PSD802G1V-B-20UI Datasheet PDF : 110 Pages
| |||
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
70
PSD835G2
Table 29. Status During Power On Reset, Warm Reset and Power Down Mode
Port Configuration Power On Reset
Warm Reset Power Down Mode
MCU I/O
Input Mode
Input Mode
Unchanged
PLD Output
Valid after internal
PSD configuration
bits are loaded
Valid
Depend on inputs to
PLD (address are
blocked in PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O Tri-stated
Tri-stated
Tri-stated
Register
Power On Reset
Warm Reset Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
Unchanged
Micro⇔Cells Flip
Flop status
Cleared to “0” by
internal power on
reset
Depend on .re and Depend on .re and
.pr equations
.pr equations
VM Register*
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Initialized based on Unchanged
the selection in
PSDsoft
Configuration Menu.
All other registers Cleared to “0”
Cleared to “0”
Unchanged
*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.
**
9.5.3.4 Reset of Flash Erase and Programming Cycles
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 µs) time.
9.6 Programming In-Circuit using the JTAG-ISP Interface
The JTAG-ISP interface on the PSD835G2 can be enabled on Port E (see Table 30). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
circuit board and programmed using JTAG-ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See ST Application Note AN1153 for more details on JTAG In-System-Programming.
Table 30. JTAG Port Signals
Port E Pin JTAG Signals
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
Description
Mode Select
Clock
Serial Data In
Serial Data Out
Status
Error Flag
Share Link: 