PSD805G1-C-90U 查看數據表（PDF） - STMicroelectronics
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PSD805G1-C-90U Datasheet PDF : 110 Pages
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PSD8XX Family
PSD835G2
PSD835G2 AC/DC Parameters – GPLD Timing Parameters
(5 V ± 10% Versions)
GPLD Combinatorial Timing (5 V ± 10%)
-70
Symbol
Parameter
Conditions Min Max
t PD
GPLD Input Pin/Feedback to
GPLD Combinatorial Output
20
t EA
GPLD Input to GPLD
Output Enable
21
t ER
GPLD Input to GPLD
Output Disable
21
tARP GPLD Register Clear or
Preset Delay
21
tARPW GPLD Register Clear or
Preset Pulse Width
10
tARD GPLD Array Delay
Any
Micro⇔Cell
11
NOTE: 1. Fast Slew Rate output available on Port C and F.
-90
Min Max
Slew
PT TURBO Rate
Aloc OFF (Note 1) Unit
25 Add 2 Add 12 Sub 2 ns
26
Add 12 Sub 2 ns
26
Add 12 Sub 2 ns
26
Add 12 Sub 2 ns
20
Add 12
ns
16 Add 2
ns
GPLD Micro⇔Cell Synchronous Clock Mode Timing (5 V ± 10% Versions)
-70
-90
Symbol
Parameter
Conditions
Min Max Min Max
Slew
PT TURBO Rate
Aloc OFF (Note 1) Unit
fMAX
tS
tH
t CH
t CL
t CO
t ARD
t MIN
Maximum Frequency
External Feedback
1/(tS + t CO )
34.4
30.30
MHz
Maximum Frequency
Internal Feedback
( fCNT)
Maximum Frequency
Pipelined Data
1/(tS + t CO –10)
1/(tCH + t CL)
52.6
43.48
83.3
50.00
MHz
MHz
Input Setup Time
14
15
Add 2 Add 12
ns
Input Hold Time
0
0
ns
Clock High Time
Clock Input
6
10
ns
Clock Low Time
Clock Input
6
10
ns
Clock to Output Delay Clock Input
15
18
Sub 2 ns
GPLD Array Delay
Any Micro⇔Cell
11
16 Add 2
ns
Minimum Clock Period tCH + t CL (Note 2) 12
20
ns
NOTES: 1. Fast Slew Rate output available on Port C and F.
2. CLKIN tCLCL = tCH + tCL.
78
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