ST92T141K4D0 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
ST92T141K4D0 Datasheet PDF : 179 Pages
| |||
ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
Reset Value: xx00 x111
7
0
-
- MX1 MX0 - DX2 DX1 DX0
Bit 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 15 PLL Multiplication Factors for
multiplier settings.
Bit 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 16 Divider Configuration for divider
settings.
Table 15. PLL Multiplication Factors
MX1
1
0
1
0
MX0
0
0
1
1
CLOCK2 x
14
10
8
6
Table 16. Divider Configuration
DX2 DX1 DX0
CK
0
0
0
PLL CLOCK/1
0
0
1
PLL CLOCK/2
0
1
0
PLL CLOCK/3
0
1
1
PLL CLOCK/4
1
0
0
PLL CLOCK/5
1
0
1
PLL CLOCK/6
1
1
0
PLL CLOCK/7
1
1
1
CLOCK2
(PLL OFF, Reset State)
Figure 31. RCCU General Timing
PLL turned on by user
PLL selected by user
rSeqTuOePst(*)
External
RESET
Xtal
clock
Multiplier
clock
Internal
reset
INTCLK
(*) WUIMU
(**) +/- 1 TXtal
Xtal/2 PLL
Xtal/2 PLL
20478xTXtal(**)
PLL
Lock-in
4 xTsys
time
10239*CLOCK2PLL
Lock-in
Quartz
time
start-up
Exit from RESET
STOP
Acknowledged
Switch to
PLL clock
71/179
1
Share Link: 