ST92163 - RESET AND CLOCK CONTROL UNIT (RCCU)
5.3 CLOCK MANAGEMENT
The various programmable features and operating modes of the CCU are handled by four registers:
– MODER (Mode Register)
This is a System Register (R235, Group E).
– CLK_FLAG (Clock Flag Register)
This is a Paged Register (R242, Page 55).
The input clock divide-by-two and the CPU clock
prescaler factors are handled by this register.
This register contains various status flags, as
well as control bits for clock selection.
– CLKCTL (Clock Control Register)
This is a Paged Register (R240, Page 55).
The low power modes and the interpretation of
the HALT instruction are handled by this register.
– PLLCONF (PLL Configuration Register)
This is a Paged Register (R246, Page 55).
The PLL multiplication and division factors are
programmed in this register.
Figure 36. Clock Control Unit Programming
XTSTO P
(CLK_FLAG)
DIV2
(MODER)
CSU_CKSEL
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
1/16
0
PLL
0
Quartz
oscillator
x
1/2 1 CLOCK2 6/8/10/14
1/N
1
CLOCK1
Internal
RC
oscillator
1/16
OUTPLL_2
0
(USB CLOCK)
1 CK_AF
WFI and LPOWFI=1 and WFI_CKSEL = 1
MX(1:0) DX(2:0)
(PLLCONF)
0
0
INTCLK
1
1
to
Peripherals
and
CPU Clock Prescaler
XT_DIV16 CKAF_ST
(CLK_FLAG)
Wait for Interrupt and Low Power Modes:
LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.
WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.
XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.
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