PSD811G3-C-12JI 查看數據表（PDF） - STMicroelectronics

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PSD811G3-C-12JI

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD835G2

The

PSD835G2

Functional

Blocks

(cont.)

PSD8XX Family

9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)

Power Down Mode

By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.

The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive

for fifteen CLKIN (pin PD1) clock periods.

The following should be kept in mind when the PSD is in Power Down Mode:

• If the address strobe starts pulsing again, the PSD will return to normal operation.

The PSD will also return to normal operation if either the CSI input returns low or the

Reset input returns high.

• The MCU address/data bus is blocked from all memories and PLDs.

• Various signals can be blocked (prior to Power Down Mode) from entering the PLDs

by setting the appropriate bits in the PMMR registers. The blocked signals include

MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from

the PLDs will not block CLKIN from the APD unit.

• All PSD memories enter Standby Mode and are drawing standby current. However,

the PLDs and I/O ports do not go into Standby Mode because you don’t want to

have to wait for the logic and I/O to “wake-up” before their outputs can change. See

Table 25 for Power Down Mode effects on PSD ports.

• Typical standby current is 50 µA for 5 V parts. This standby current value assumes

that there are no transitions on any PLD input.

Table 25. Power Down Mode’s Effect on

Ports

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

Address Out

Undefined

Data Port

Three-State

Peripheral I/O

Three-State

Table 26. PSD835G2 Timing and Standby Current During Power

Down Mode

Mode

PLD

Propagation

Delay

Memory

Access

Time

Access

Recovery Time

to Normal

Access

5V VCC,

Typical

Standby

Current

Power Down

Normal tpd

(Note 1)

No Access

tLVDV

50 µA

(Note 2)

NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this

mode is based only on the Turbo Bit.

2. Typical current consumption assuming no PLD inputs are changing state and

the PLD Turbo bit is off.

65

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