PSD814G3-C-20B81 查看數據表（PDF） - STMicroelectronics

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PSD814G3-C-20B81

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD835G2

The

PSD835G2

Functional

Blocks

(cont.)

PSD8XX Family

9.6.1 Standard JTAG Signals

The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three

different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are

inputs, waiting for a serial command from an external JTAG controller device (such as

FlashLink or Automated Test Equipment). When the enabling command is received from

the external JTAG controller, TDO becomes an output and the JTAG channel is fully

functional inside the PSD. The same command that enables the JTAG channel may

optionally enable the two additional JTAG pins, TSTAT and TERR.

The following symbolic logic equation specifies the conditions enabling the four basic

JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of

discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins

are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD

I/O.

JTAG_ON =

PSDsoft_enabled +

/* An NVM configuration bit inside the PSD is set by the designer

in the PSDsoft Configuration utility. This dedicates the pins for

JTAG at all times (compliant with IEEE 1149.1) */

Microcontroller_enabled +

/* The microcontroller can set a bit at run-time by writing to the

PSD register, JTAG Enable. This register is located at address

CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this

register will enable the pins for JTAG use. This bit is cleared

by a PSD reset or the microcontroller. See Table 31 for bit

definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT) inside the PSD can be used to

enable the JTAG pins. This PT has the reserved name

JTAGSEL. Once defined as a node in PSDabel, the designer

can write an equation for JTAGSEL. This method is used when

the Port E JTAG pins are multiplexed with other I/O signals.

It is recommended to logically tie the node JTAGSEL to the

JEN\ signal on the Flashlink cable when multiplexing JTAG

signals. See Application Note 54 for details.

Table 31. JTAG Enable Register

JTAG Enable

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

*

*

*

*

*

*Bits 1-7 are not used and should set to 0.

Bit definitions:

JTAG_ENABLE 1 = JTAG Port is Enabled.

0 = JTAG Port is Disabled.

Bit 2

*

Bit 1

*

Bit 0

JTAG_ENABLE

NOTE:

The state of the PSD reset input signal will not interrupt (or prevent) JTAG operations if

the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, the

PSD reset input will prevent or interrupt JTAG operations if the JTAG enable register is

used to enable the JTAG pins.

71

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