PSD802G3-C-12UI 查看數據表（PDF） - STMicroelectronics
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PSD802G3-C-12UI Datasheet PDF : 110 Pages
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PSD835G2
PSD8XX Family
PSD835G2 DC Characteristics (5 V ± 10% Versions)
Symbol
Parameter
Conditions
Min
VCC
VIH
VIL
VIH1
VIL1
VHYS
VLKO
VOL
VOH
VOH1
VSBY
ISBY
IIDLE
VDF
ISB
ILI
ILO
IO
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
VCC Min for Flash Erase and Program
Output Low Voltage
Output High Voltage Except VSTBY On
Output High Voltage VSTBY On
SRAM Standby Voltage
SRAM Standby Current (VSTBY Pin)
Idle Current (VSTBY Pin)
SRAM Data Retention Voltage
Standby Supply Current for Power
Down Mode
Input Leakage Current
Output Leakage Current
Output Current
ICC (DC) Operating Supply
(Note 5) Current
PLD Only
Flash
SRAM
All Speeds
4.5
4.5 V < VCC < 5.5 V
4.5 V < VCC < 5.5 V
(Note 1)
(Note 1)
2
– .5
.8 VCC
–.5
0.3
2.5
IOL = 20 µA, VCC = 4.5 V
IOL = 8 mA, VCC = 4.5 V
IOH = –20 µA, VCC = 4.5 V
4.4
IOH = –2 mA, VCC = 4.5 V
IOH1 = –1 µA
2.4
VSBY – 0.8
2.0
VCC = 0 V
VCC > VSBY
Only on VSTBY
– 0.1
2
CSI > VCC –0.3 V
(Notes 2, 3 and 5)
VSS < VIN < VCC
–1
0.45 < VIN < VCC
–10
Refer to IOL and IOH in
the VOL and VOH row
PLD_TURBO = OFF,
f = 0 MHz (Note 3)
PLD_TURBO = ON,
f = 0 MHz
During Flash Write/Erase
Only
Read Only, f = 0 MHz
f = 0 MHz
ICC (AC)
(Note 5)
PLD AC Base
FLASH AC Adder
SRAM AC Adder
Fig. 32
(Note 4)
NOTE: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.
2. CSI deselected or internal Power Down mode is active.
3. PLD is in non-turbo mode and none of the inputs are switching
4. Refer to Figure 32 for PLD current calculation.
5. IO = 0 mA
Typ
5
0.01
0.25
4.49
3.9
0.5
100
±.1
±5
0
400
15
0
0
2.5
1.5
Max
5.5
VCC +.5
0.8
VCC +.5
.2 VCC –.1
4.2
0.1
0.45
VCC
1
0.1
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
200
µA
1
µA
10
µA
mA
700
µA/PT
30
mA
0
mA
0
mA
3.5
mA/MHz
3.0
mA/MHz
77
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