PSD954F3V70MIT 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

PSD954F3V70MIT

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PAGE REGISTER

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included in the Sector Select (FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all 8 page

register bits are needed for memory paging, then

these bits may be used in the CPLD for general

logic. See Application Note AN1154.

Figure 12 shows the Page Register. The eight flip-

flops in the register are connected to the internal

data bus D0-D7. The MCU can write to or read

from the Page Register. The Page Register can be

accessed at address location CSIOP + E0h.

Figure 12. Page Register

RESET

D0

Q0

D1

Q1

D0- D7 D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

R/W

D7

Q7

PAGE

REGISTER

PGR0

PGR1

PGR2

PGR3

PGR4

PGR5

PGR6

PGR7

DPLD

AND

CPLD

PLD

INTERNAL

SELECTS

AND LOGIC

AI02871B

32/110

Share Link: