PSD954F3V70UI 查看數據表（PDF） - STMicroelectronics
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PSD954F3V70UI Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)
38.4
26.32
21.27
MHz
fMAXA
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
27.78
MHz
Maximum
Frequency
Pipelined
Data
1/(tCHA+tCLA)
71.4
41.67
35.71
MHz
tSA
Input Setup
Time
7
8
12
+ 2 + 10
ns
tHA
Input Hold
Time
8
12
14
ns
tCHA
Clock Input
High Time
9
12
15
+ 10
ns
tCLA
Clock Input
Low Time
9
12
15
+ 10
ns
tCOA
Clock to
Output Delay
21
30
37
+ 10 – 2 ns
tARDA
CPLD Array
Delay
Any macrocell
11
16
22 + 2
ns
tMINA
Minimum
Clock Period
1/fCNTA
16
28
39
ns
84/110
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