PSD934210MT 查看數據表（PDF） - STMicroelectronics
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PSD934210MT
STMicroelectronics
PSD934210MT Datasheet PDF : 89 Pages
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PSD834F2V
Table 52. Reset (Reset) Timing
Symbol
Parameter
Conditions
Min
tNLNH
RESET Active Low Time 1
300
tNLNH–PO
Power On Reset Active Low Time
1
tNLNH–A
Warm Reset 2
25
tOPR
RESET High to Operational Device
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.
Max
Unit
ns
ms
µs
300
ns
Table 53. VSTBYON Timing
Symbol
Parameter
tBVBH
VSTBY Detection to VSTBYON Output High
tBXBL
VSTBY Off Detection to VSTBYON Output
Low
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Conditions
(Note 1)
(Note 1)
Min
Typ
Max Unit
20
µs
20
µs
Table 54. ISC Timing
Symbol
Parameter
Conditions
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
tISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note 1)
tISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note 1)
tISCCFP Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
tISCCHP Clock (TCK, PC1) High Time (PLD only)
(Note 2)
tISCCLP Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
tISCPSU ISC Port Set Up Time
tISCPH ISC Port Hold Up Time
tISCPCO ISC Port Clock to Output
tISCPZV ISC Port High-Impedance to Valid Output
tISCPVZ
ISC Port Valid Output to
High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
-10
-15
-20
Unit
Min Max Min Max Min Max
12
10
9 MHz
40
45
51
ns
40
45
51
ns
2
2
2 MHz
240
240
240
ns
240
240
240
ns
12
13
15
ns
5
5
5
ns
30
36
40 ns
30
36
40 ns
30
36
40 ns
80/89
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