PSD933412UIT 查看數據表（PDF） - STMicroelectronics
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PSD933412UIT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 46. DC Characteristics (3V devices)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIH
High Level Input Voltage
3.0 V < VCC < 3.6 V
0.7VCC
VCC +0.5
V
VIL
Low Level Input Voltage
3.0 V < VCC < 3.6 V
–0.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
0.8VCC
VCC +0.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–0.5
0.2VCC –0.1 V
VHYS
Reset Pin Hysteresis
0.3
V
VLKO
VCC (min) for Flash Erase and
Program
1.5
2.2
V
VOL
Output Low Voltage
IOL = 20µA, VCC = 3.0 V
IOL = 4mA, VCC = 3.0 V
0.01
0.1
V
0.15
0.45
V
VOH
Output High Voltage Except
VSTBY On
IOH = –20µA, VCC = 3.0 V
IOH = –1mA, VCC = 3.0 V
2.9
2.7
2.99
2.8
V
V
VOH1
Output High Voltage VSTBY On
IOH1 = 1µA
VSTBY – 0.8
V
VSTBY SRAM Stand-by Voltage
2.0
VCC
V
ISTBY
SRAM Stand-by Current
VCC = 0 V
0.5
1
µA
IIDLE
Idle Current (VSTBY input)
VCC > VSTBY
–0.1
0.1
µA
VDF
SRAM Data Retention Voltage
Only on VSTBY
2
V
ISB
Stand-by Supply Current
for Power-down Mode
CSI >VCC –0.3 V (Notes 2,3)
25
100
µA
ILI
Input Leakage Current
VSS < VIN < VCC
–1
±0.1
1
µA
ILO
Output Leakage Current
0.45 < VIN < VCC
–10
±5
10
µA
ICC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
Flash memory
PLD_TURBO = Off,
f = 0 MHz (Note 3)
PLD_TURBO = On,
f = 0 MHz
During Flash memory
WRITE/Erase Only
Read only, f = 0 MHz
0
µA/PT
200
400
µA/PT
10
25
mA
0
0
mA
SRAM
f = 0 MHz
0
0
mA
PLD AC Adder
note 4
ICC (AC) Flash memory AC Adder
(Note 5)
SRAM AC Adder
1.5
2.0
mA/
MHz
0.8
1.5
mA/
MHz
Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal PD is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Figure 36., page 72 for the PLD current calculation.
5. IOUT = 0mA
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