PSD934490MIT 查看數據表（PDF） - STMicroelectronics

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PSD934490MIT

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 70. ISC Timing (3V devices)

Symbol

Parameter

Conditions

tISCCF

Clock (TCK, PC1) Frequency (except for

PLD)

(Note 1)

tISCCH

Clock (TCK, PC1) High Time (except for

PLD)

(Note 1)

tISCCL

Clock (TCK, PC1) Low Time (except for

PLD)

(Note 1)

tISCCFP Clock (TCK, PC1) Frequency (PLD only)

(Note 2)

tISCCHP Clock (TCK, PC1) High Time (PLD only)

(Note 2)

tISCCLP Clock (TCK, PC1) Low Time (PLD only)

(Note 2)

tISCPSU ISC Port Set Up Time

tISCPH ISC Port Hold Up Time

tISCPCO ISC Port Clock to Output

tISCPZV ISC Port High-Impedance to Valid Output

tISCPVZ

ISC Port Valid Output to

High-Impedance

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

-12

-15

-20

Unit

Min Max Min Max Min Max

12

10

9 MHz

40

45

51

ns

40

45

51

ns

2

2

2 MHz

240

240

240

ns

240

240

240

ns

12

13

15

ns

5

5

5

ns

30

36

40 ns

30

36

40 ns

30

36

40 ns

Table 71. Power-down Timing (5V devices)

Symbol

Parameter

Conditions

tLVDV

ALE Access Time from Power-down

tCLWH

Maximum Delay from

APD Enable to Internal PDN Valid

Signal

Note: 1. tCLCL is the period of CLKIN (PD1).

Using CLKIN

(PD1)

-70

-90

-15

Unit

Min Max Min Max Min Max

80

90

150 ns

15 * tCLCL1

µs

Table 72. Power-down Timing (3V devices)

Symbol

Parameter

Conditions

tLVDV

ALE Access Time from Power-down

tCLWH

Maximum Delay from APD Enable to

Internal PDN Valid Signal

Note: 1. tCLCL is the period of CLKIN (PD1).

Using CLKIN

(PD1)

-12

-15

-20

Unit

Min Max Min Max Min Max

145

150

200 ns

15 * tCLCL1

µs

99/110

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