PSD935G1-C-90MI 查看數據表（PDF） - STMicroelectronics
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PSD935G1-C-90MI Datasheet PDF : 91 Pages
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PSD9XX Family
The
PSD935G2
Functional
Blocks
(cont.)
PSD935G2
Table 17. Port Operating Mode Settings
Mode
Defined In
PSDsoft
Control
Register
Setting
MCU I/O
Declare
pins only
0
(Note 1)
PLD I/O
Declare pins
and logic or chip
NA
select equations
Data Port
(Port F)
Selected for
MCU with
non-mux bus
NA
Address Out
(Port E, F, G)
Declare
pins only
1
Address In
Declare pins
(Port A,B,C,D,F)
NA
JTAG ISP
Declare pins
only
NA
Direction
Register
Setting
1 = output,
0 = input
NA
1
NA
NA
VM
Register
Setting
NA
NA
NA
NA
NA
NA
*NA = Not Applicable
NOTE: 1. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD935G2 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD935G2 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing
to the corresponding bit in the Direction Register. See the subsection on the Direction
Register in the “Port Registers” section. When the pin is configured as an output, the
content of the Data Out Register drives the pin. When configured as an input, the
microcontroller can read the port input through the Data In buffer. See Figure 20.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro⇔Cells, and/or
as an output from the GPLD. The corresponding bit in the Direction Register must not be
set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified
in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
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