R5F212E2DFP 查看數據表（PDF） - Renesas Electronics

零件编号

产品描述 (功能)

生产厂家

R5F212E2DFP

RENESAS MCU R8C FAMILY / R8C/2x SERIES

Renesas Electronics 

R8C/2E Group, R8C/2F Group

13. Watchdog Timer

13. Watchdog Timer

The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is

recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows

selection of count source protection mode enable or disable.

Table 13.1 lists the Specifications for Watchdog Timer.

Refer to 5.5 Watchdog Timer Reset for details on the watchdog timer.

Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows the Registers WDTR, WDTS, and WDC

and Figure 13.3 shows the Registers CSPR and OFS.

Table 13.1 Specifications for Watchdog Timer

Item

Count source

Count operation

Count start condition

Count stop condition

Reset condition of

watchdog timer

Operation at the time

of underflow

Select functions

Count Source Protection Mode Disabled Count Source Protection Mode Enabled

CPU clock

Low-speed on-chip oscillator clock

Decrement

Either of the following can be selected

• After reset, count starts automatically

• Count starts by writing to WDTS register

Stop mode, wait mode

None

• Reset

• Write 00h to the WDTR register before writing FFh

• Underflow

Watchdog timer interrupt or watchdog Watchdog timer reset

timer reset

• Division ratio of prescaler

Selected by the WDC7 bit in the WDC register

• Count source protection mode

Whether count source protection mode is enabled or disabled after a reset can

be selected by the CSPROINI bit in the OFS register (flash memory). If count

source protection mode is disabled after a reset, it can be enabled or disabled

by the CSPRO bit in the CSPR register (program).

• Starts or stops of the watchdog timer after a reset

Selected by the WDTON bit in the OFS register (flash memory).

Prescaler

1/16

WDC7 = 0

CSPRO = 0

CPU clock

1/128

Write to WDTR register

Internal reset signal

WDC7 = 1

fOCO-S

CSPRO = 1

Watchdog timer

Set to

7FFFh(1)

PM12 = 0

Watchdog timer

interrupt request

PM12 = 1

Watchdog

timer reset

CSPRO: Bit in CSPR register

WDC7: Bit in WDC register

PM12: Bit in PM1 register

NOTE:

1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.

Figure 13.1 Block Diagram of Watchdog Timer

Rev.1.00 Dec 14, 2007 Page 115 of 332

REJ09B0349-0100

Share Link: