STG3005A2STR 查看數據表（PDF） - STMicroelectronics

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STG3005A2STR

128-BIT 3D MULTIMEDIA ACCELERATOR

STMicroelectronics 

128-BIT 3D MULTIMEDIA ACCELERATOR

8.3 TIMING DIAGRAMS

Figure 46. Poll cycle

MPCLK

MPFRAME#

MP_AD[7:0]

A0

D0

MPDTACK#

Figure 47. Poll cycle throttled by slave

MPCLK

MPFRAME#

MP_AD[7:0]

A0

D0

MPDTACK#

Figure 48. CPU write cycle

MPCLK

MPFRAME#

MP_AD[7:0]

A0 A1

D

MPDTACK#

Figure 49. CPU write cycle throttled by slave

MPCLK

MPFRAME#

MP_AD[7:0]

A0 A1

D

MPDTACK#

RIVA128ZX

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