ATSAM4LS4BA-AU 查看數據表（PDF） - Atmel Corporation

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ATSAM4LS4BA-AU

ATSAM ARM-based Flash MCU

Atmel Corporation 

ATSAM4L8/L4/L2

2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.

Notations:

Cb = total capacitance of one bus line in pF

tclkpb = period of TWI peripheral bus clock

tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS)

The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI)

of TWCK.

9.10.5 JTAG Timing

Figure 9-17. JTAG Interface Signals

TCK

JTAG0

JTAG2

JTAG1

TMS/TDI

JTAG3

JTAG4

TDO

Boundary

Scan Inputs

Boundary

Scan Outputs

JTAG5

JTAG6

JTAG7

JTAG8

JTAG9

JTAG10

42023GS–SAM–03/2014

150

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