Si3000
Register 3. PLL1 Divide N1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Divider N1
Type
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
N1
N1.
Contains the (value – 1) for determining the output frequency on PLL.
Register 4. PLL1 Multiply M1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Multiplier M1
Type
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
M1
M1.
Contains the (value – 1) for determining the output frequency on PLL.
22
Rev. 1.4