SST58SD032-70-C-P1H 查看數據表（PDF） - Silicon Storage Technology

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SST58SD032-70-C-P1H

ATA-Disk Chip

Silicon Storage Technology

SST58SD032-70-C-P1H Datasheet PDF : 40 Pages

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ATA-Disk Chip

SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192

SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192

Data Sheet

3.1.2.9 Status & Alternate Status Registers (Read Only)

These registers return the ADC status when read by the host. Reading the Status register does clear a pending

interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows:

BUSY

RDY

DWF

DSC

DRQ

CORR

ERR

Bit 7 (BUSY) The busy bit is set when the ADC has access to the command buffer and registers and

the host is locked out from accessing the command register and buffer. No other bits in

this register are valid when this bit is set to a 1.

Bit 6 (RDY) RDY indicates whether the device is capable of performing ADC operations. This bit is

cleared at power up and remains cleared until the ADC is ready to accept a command.

Bit 5 (DWF) This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC) This bit is set when the ADC is ready.

Bit 3 (DRQ) The Data Request is set when the ADC requires that information be transferred either to

or from the host through the Data register.

Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has

been corrected. This condition does not terminate a multi-sector Read operation.

Bit 1 (IDX) This bit is always set to 0.

Bit 0 (ERR)

This bit is set when the previous command has ended in some type of error. The bits in

the Error register contain additional information describing the error. It is recommended

that media access commands (such as Read Sectors and Write Sectors) that end with

an error condition should have the address of the first sector in error in the command

block registers.

3.1.2.10 Device Control Register (Write Only)

This register is used to control the ADC interrupt request and to issue a software Reset. This register can be written

to even if the device is BUSY. The bits are defined as follows:

SW Rst

-IEn

Bit 7

This bit is an X (don’t care).

Bit 6

This bit is an X (don’t care).

Bit 5

This bit is an X (don’t care).

Bit 4

This bit is an X (don’t care).

Bit 3

This bit is ignored by the ADC.

Bit 2 (SW Rst) This bit is set to 1 in order to force the ADC to perform a software Reset operation. The

chip remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn) The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts

from the ADC are disabled. This bit is Reset to 0 at power on and Reset.

Bit 0

This bit is ignored by the ADC.

S71167-05-000 9/01 391

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