PIC16C7X
14.3 Reset
Applicable Devices
72 73 73A 74 74A 76 77
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR) (PIC16C72/73A/74A/76/
77)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 14-5 and Table 14-6. These bits are used in soft-
ware to determine the nature of the reset. See
Table 14-8 for a full description of reset states of all reg-
isters.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 14-8.
The PIC16C72/73A/74A/76/77 have a MCLR noise fil-
ter in the MCLR reset path. The filter will detect and
ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
VDD
SLEEP
WDT WDT
Module Time-out
Reset
VDD rise
detect
(2) Power-on Reset
Brown-out
Reset BODEN
OSC1
OST/PWRT
OST
10-bit Ripple counter
(1) PWRT
On-chip
RC OSC
10-bit Ripple counter
S
Chip_Reset
R
Q
Enable PWRT
(3)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77.
3: See Table 14-3 and Table 14-4 for time-out situations.
© 1997 Microchip Technology Inc.
DS30390E-page 133