PIC16C76-04/SP 查看數據表（PDF） - Microchip Technology

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PIC16C76-04/SP

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C7X

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: Value on all

POR, other resets

BOR

(2)

Bank 0

00h(4)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx uuuu uuuu

02h(4)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

03h(4)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

04h(4)

FSR

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h

PORTA

—

— PORTA Data Latch when written: PORTA pins when read

--0x 0000 --0u 0000

06h

PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

07h

08h(5)

09h(5)

0Ah(1,4)

0Bh(4)

0Ch

PORTC

PORTD

PORTE

PCLATH

INTCON

PIR1

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

PORTD Data Latch when written: PORTD pins when read

xxxx xxxx uuuu uuuu

—

—

—

—

—

RE2

RE1

RE0 ---- -xxx ---- -uuu

—

—

— Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

GIE

PSPIF(3)

PEIE

ADIF

T0IE

RCIF

INTE

TXIF

RBIE

SSPIF

T0IF

CCP1IF

INTF

TMR2IF

RBIF 0000 000x 0000 000u

TMR1IF 0000 0000 0000 0000

0Dh

PIR2

—

—

—

–

—

—

—

CCP2IF ---- ---0 ---- ---0

0Eh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h

T1CON

—

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000 0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON WCOL SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h

CCPR1L Capture/Compare/PWM Register1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

—

CCP1X

CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D 0000 -00x 0000 -00x

19h

TXREG USART Transmit Data Register

0000 0000 0000 0000

1Ah

RCREG USART Receive Data Register

0000 0000 0000 0000

1Bh

CCPR2L Capture/Compare/PWM Register2 (LSB)

xxxx xxxx uuuu uuuu

1Ch

CCPR2H Capture/Compare/PWM Register2 (MSB)

xxxx xxxx uuuu uuuu

1Dh

CCP2CON

—

—

CCP2X

CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

1Eh

ADRES A/D Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0 ADCS1 ADCS0 CHS2

CHS1

CHS0 GO/DONE

—

ADON 0000 00-0 0000 00-0

Legend:

Note 1:

2:

3:

4:

5:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.

These registers can be addressed from any bank.

PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.

© 1997 Microchip Technology Inc.

DS30390E-page 27

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