PIC16LC73AT-20ESO 查看數據表（PDF） - Microchip Technology

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PIC16LC73AT-20ESO

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C7X

4.2.2.3

INTCON REGISTER

Applicable Devices

72 73 73A 74 74A 76 77

The INTCON Register is a readable and writable regis-

ter which contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

FIGURE 4-9: INTCON REGISTER

(ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

R/W-0

GIE

bit7

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

bit 7:

GIE:(1) Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

bit0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 6:

PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5:

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4:

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3:

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2:

T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1:

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0:

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Note 1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit

may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine.

Refer to Section 14.5 for a detailed description.

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to

enabling an interrupt.

DS30390E-page 32

© 1997 Microchip Technology Inc.

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