PIC16LC73T-20/SO 查看數據表（PDF） - Microchip Technology

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PIC16LC73T-20/SO

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

5.2 PORTB and TRISB Registers

Applicable Devices

72 73 73A 74 74A 76 77

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a bit

in the TRISB register puts the corresponding output

driver in a hi-impedance input mode. Clearing a bit in

the TRISB register puts the contents of the output latch

on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF

CLRF

BSF

MOVLW

MOVWF

STATUS, RP0

PORTB

STATUS, RP0

0xCF

TRISB

;

; Initialize PORTB by

; clearing output

; data latches

; Select Bank 1

; Value used to

; initialize data

; direction

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU (OPTION<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

FIGURE 5-3:

RBPU(2)

Data bus

BLOCK DIAGRAM OF

RB3:RB0 PINS

VDD

Data Latch

DQ

P

weak

pull-up

WR Port

WR TRIS

CK

TRIS Latch

DQ

CK

TTL

Input

Buffer

I/O

pin(1)

PIC16C7X

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e. any RB7:RB4 pin con-

figured as an output is excluded from the interrupt on

change comparison). The input pins (of RB7:RB4) are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RB Port Change Inter-

rupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with soft-

ware configurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. Refer to the Embedded

Control Handbook, "Implementing Wake-Up on Key

Stroke" (AN552).

Note:

For the PIC16C73/74, if a change on the

I/O pin should occur when the read opera-

tion is being executed (start of the Q2

cycle), then interrupt flag bit RBIF may not

get set.

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

RD TRIS

RD Port

QD

EN

RB0/INT

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION<7>).

© 1997 Microchip Technology Inc.

DS30390E-page 45

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