PIC16C7X
Applicable Devices
72 73 73A 74 74A 76 77
11.2 SPI Mode for PIC16C72/73/73A/74/74A
This section contains register definitions and opera-
tional characteristics of the SPI module for the
PIC16C72, PIC16C73, PIC16C73A, PIC16C74,
PIC16C74A.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
U-0
—
bit7
bit 7-6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
U-0 R-0
R-0
R-0
R-0
R-0
R-0
—
D/A
P
S
R/W
UA
BF
R = Readable bit
bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
Unimplemented: Read as '0'
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS30390E-page 78
© 1997 Microchip Technology Inc.