ST20CX 查看數據表（PDF） - STMicroelectronics

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ST20CX

Instruction Set Reference Manual

STMicroelectronics 

If the process state registers are referred to without subscripts then the current priority

is implied.

3.1.2 Other machine registers

There are several other registers which the programmer should know about, but which

are not part of the process state. These are presented in Table 3.3.

register

full name / description

ProcQueueFPtr[0]

ProcQueueFPtr[1]

ProcQueueBPtr[0]

ProcQueueBPtr[1]

ClockReg[0]

ClockReg[1]

TptrReg[0]

TptrReg[1]

TnextReg[0]

TnextReg[1]

Enables

high priority front pointer register - contains pointer to first process on the high

priority scheduling list

low priority front pointer register - contains pointer to first process on the low

priority scheduling list

high priority back pointer register - contains pointer to last process on the high

priority scheduling list

low priority back pointer register - contains pointer to last process on the low

priority scheduling list

high priority clock register - contains current value of high priority clock

low priority clock register - contains current value of low priority clock

high priority timer list pointer register - contains pointer to the first process on

the high priority timer list

low priority timer list pointer register - contains pointer to the first process on the

low priority timer list

high priority alarm register - contains the time of the first process on the high

priority timer queue

low priority alarm register - contains the time of the first process on the low

priority timer queue

trap and global interrupt enables register

Table 3.3 Other machine registers

Enables register

The Enables register contains:

• TrapEnables bits (0..15) which can be used to control the taking of traps;

• GlobalInterruptEnables bits (16..31) which are used to control timeslicing and

interruptibility. These are normally set to 1.

Bits of TrapEnables may be set using the trapenb instruction and cleared using

trapdis. Bits of GlobalInterruptEnables may be set using the instruction gintenb and

disabled using gintdis.

The contents of the Enables register are shown in Table 3.4.

ClockEnables

ClockEnables is a pair of flags which enab le the timers ClockReg to tick. Bit zero of

ClockEnables controls ClockReg[0] and bit 1 controls ClockReg[1]. In each case,

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